1. Field of the Invention
The invention relates in general to a method of forming semiconductor integrated circuits (ICs), and more particularly to a method of forming interconnections.
2. Description of the Related Art
Increasing integration of an integrated circuit (IC) device results in insufficient wafer surface for formation of desired interconnects. In accordance with a need of interconnects in a metal-oxide semiconductor (MOS) transistor that has a highly reduced dimension, an interconnect structure is necessarily designed to include at least two metal layers. These multiple metal layers are usually insulated and held by inter-metal dielectric (IMD) layers in between them. According to designed circuit architecture, these metal layers have to be electrically coupled together at certain places. A via structure formed in the IMD layer is employed for this purpose of coupling. The via structure typically includes a via hole and a conductive via plug to fill the via hole. These two metal layers on both sides of the IMD layer are electrically coupled through the conductive via plug.
FIGS. 1A to 1E are schematic, cross-sectional views, illustrating a conventional fabrication process of a interconnection. In FIG. 1A, a substrate 100 having a device structure thereon is provided. A defined metal layer 102 as a metal line is formed on the substrate 100.
In FIG. 1B, a dielectic layer 106 is formed on the substrate 100 and on the defined metal layer 102. A planarization process is performed on the dielectric layer 106 to obtain a planar surface on the dielectric layer 106. A material of the dielectric layer 106 is silicon oxide with a dielectric constant of about 4-4.9.
In FIG. 1C, the dielectric layer 106 is defined to form a via hole 108 in the dielectric layer 106 using the metal layer 102 as an etching stop layer. A conformal barrier/glue layer 107 is formed on the dielectric layer 106.
In FIG. 1D, a conductive layer 110 is formed on the barrier/glue layer 107. The barrier/glue layer 107 enhances the adhesion between the conductive layer 110 and the dielectric layer 106. The conductive layer 110 fills the via hole 108 to form a metal plug electrically coupling with the metal layer 102. A planarization process is performed to planarize the conductive layer 110.
In FIG. 1E, the conductive layer 110 and the barrier/glue layer 107 are defined to form a wiring line 110a. An interconnection is thus completed.
The metal layer 102, the dielectric layer 106 and the conductive layer 110 constitute a capacitor structure called "parasitic capacitor". Since the dielectric constant of the dielectric layer 106 is high, problems with the parasitic capacitor become more serious than before when the feature size is smaller and a distance between two metal lines is shorter than before. One of the problems is RC delay. Another of the problems is cross-talk between the metal lines. These problems decrease the performance of devices.